TI DAC3XJ8X很低功耗电16位四路2.5 GSPS DAC解决方案

TI公司的DAC37J84/DAC38J84系列是非常低功耗16位四路1.6/2.5 GSPS DAC,其JESD204B接口高达12.5Gbps,最大输入数据速率1.23GSPS, 在2.5GSPS时的功耗为1.8W,主要用在基站,发送器,宽带通信,直接数字合成(DDS)仪表,毫米波/微波骨干网,自动测试设备(ATE)和有线通信等.本文介绍了DAC37J84/DAC38J84主要特性和框图, 评估模块DAC3XJ8XEVM主要特性和简化框图,电路图,材料清单和PCB元件布局图.
The pin-compatible DAC37J84/DAC38J84 family is a very low power, 16-bit, quad-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface up to 12.5 Gbps. The maximum input data rate is 1.23 GSPS. The DAC37J84/DAC38J84 family is also pin-compatible with the 16-bit, dual-channel, 1.6/2.5GSPS DAC37J82/DAC38J82 family.
Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.
The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement. A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.
The DAC37J84/DAC38J84 family is packaged in a 10×10mm 144-pin flip-chip BGA. The DAC37J84/ DAC38J84 family is specified ove...