NXP高速ADC解决方案

Keywords: high speed ADC   ADC1x13D080    JESD204A data convter
摘要：恩智浦已设计了一个USB供电的演示板，演示互操作性Lattice的ECP3 FPGA的JESD204A串行接口应用恩智浦的ADC。
基本特性：
A single USB cable will allow to supply the board and to communicate with the FPGA &the ADC thanks to dedicated software running on a PC. It is then possible to load thedata from the ADC through the FPGA and have an overview of the ADC features and performance, in the frequency range of [0; 30]MHz. By default an on-board oscillator is used to generate the sampling frequency, but it is optionally possible to use an external clock to have more flexibility and a better jitter performance.
方案描述：
The list of equipment needed is as follows:
 A PC
 A USB cable
 A low jitter sine wave generator
 A band-pass filter in case the sine wave is not pure enough
 2 SMA-SMA cables if a filter is used, 1 cable if no filter
 The NXP demo board
In addition, dedicated software is necessary to drive the FPGA & the ADC from the PC.
This software has been developed thanks to LabView, which means that at least the LabView Runtime needs to be installed on the Laptop PC or the LabView environment itself (v8.5).
On this demo board, the sampling frequency is by default defined by an on-board oscillator, which generates FS = 60Mhz. So you can input a sine wave between 0Hz and 30MHz. Although the ADC1x13D080 datasheet mentions 65Mhz as the minimum frequency, we have decided to use a 60Mhz oscillator since the Abracon ASE oscillator has a very good jitter compared to other oscillators but it is unfortunately not easily available for an output frequency higher than 60Mhz. It is then possible to demonstrate good SNR performance (in the range of 72dB) over the [0;30]MHz band.
参考原理图

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