Lattice LatticeECP3 HDR-60高清视频开发方案

Lattice 公司的HDR-60高清视频开发板是采用第三代LatticeECP3器件LatticeECP3™-70 FPGA,是低成本评估和演示平台,可以进行评估,测试和调试图像信号处理,和NanoVesta Head Board一起,组成了视频照相机开发套件.采用的传感器是Aptina公司的A-1000 HDRI 传感器,主要应用在安全监视照乡机和汽车照相机,以太网IP照相机, Teradek H.264压缩模块的评估.本文介绍了LatticeECP3器件主要特性和方框图,以及HDR-60高清视频开发板主要特性,方框图,详细电路图和元件布局图.
The LatticeECP3?(EConomy Plus Third generation) family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications.
The LatticeECP3 device family expands look-up-table (LUT) capacity to 149K logic elements and supports up to 586 user I/Os. The LatticeECP3 device family also offers up to 320 18x18 multipliers and a wide range of parallel I/O standards.
The LatticeECP3 FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP3 devices utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and dual-boot capabilities.
The pre-engineered source synchronous logic implemented in the LatticeECP3 device family supports a broad range of interface standards, including DDR3, XGMII and 7:1 LVDS.
The LatticeECP3 device family also features high speed SERDES with dedicated PCS functions. High jitter tolerance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular data protocols including PCI Exp...