TI CDCDB400四输出LP-HCSLPCIe Gen 1-5时钟缓冲器解决方案

TI公司的CDCDB400是四输出LP-HCSLDB800ZL兼容的时钟缓冲器,用于CC, SRNS, 或SRIS架构的PCIe Gen 1-5,快速通道互联(QPI),UPI,SAS和SATA接口.SMBus接口和四个输出使得引脚允许可单独配置和控制所有四个输出.CDCDB400是DB800ZL派生缓冲器,满足或超过DB800ZL指标的系统参数.器件还满足或超过DB2000Q指标的系统参数.器件的4个LP-HCSL输出有可编程的集成85-Ω(默认)或100-Ω差分输出端,4个硬件输出使能(OE#)控制,PCIE Gen5滤波器后的附加相位抖动小于25 fs,RMS(最大值),DB2000Q滤波器后的附加的位抖动小于38fs RMS(最大值).器件支持PCIe Gen 4 和Gen 5共同时钟(CC)和单个基准(IR)架构.器件和扩频兼容,输出到输出的偏离小于50ps,输入到输入的延迟小于3ns,故障安全输入,可编输出转换速率控制,有三个可选择SMBus地址,3.3V核和IO电源,硬件控制的低功耗模式(PD#),最大电流损耗为46mA,5-mm × 5-mm 32引脚 VQFN封装.主要用在微服务器和塔式服务器,存储局域网和主总线适配卡,网络连接存储,硬件加速器,机架式服务器,通信交换,模块上的计算机,CT和PET扫描仪和坚固耐用的PC笔记本电脑.本文介绍了CDCDB400主要特性,系统框图和功能框图, 典型应用以及评估模块CDCDB400 EVM主要特性, 快速起动建立图,电路图和材料清单.

The CDCDB400 is a 4-output LP-HCSL, DB800ZLcompliant,clock buffer capable of distributing thereference clock for PCIe Gen 1-5, QuickPathInterconnect (QPI), UPI, SAS, and SATA interfacesin CC, SRNS, or SRIS architectures. The SMBusinterface and four output enable pins allow theconfiguration and control of all four outputsindividually. The CDCDB400 is a DB800ZL derivativebuffer and meets or exceeds the system parameters

in the DB800ZL specification. The device alsomeets or exceeds the parameters in the DB2000Qspecification. The CDCDB400 is packaged in a 5-mm× 5-mm, 32-pin VQFN package.

CDCDB400主要特性:

• 4 LP-HCSL outputs with programmable integrated85-Ω (default) or 100-Ω differential outputterminations

• 4 hardware output enable (OE#) controls

• Additive phase jitter after PCIE Gen5 filter: < 25 fs,RMS (maximum)

• Additive phase jitter after DB2000Q filter: < 38 fs...