Cirrus CS42L37低功耗音频CODEC方案

Cirrus公司的CS42L37是高度集成的低功耗音频和电话CODEC,主要用于手持应用如智能手机和超小型移动计算机. CS42L37具有灵活的时钟架构,时钟频率有6, 12, 24, 13, 26, 19.2, 或38.4 MHz,具有立体声ADC,支持双路模拟或数字MIC,双路MIC偏压发生器,4个DAC耦合到5个输出. 立体声ADC动态范围91dB,THD+N为-85dB,2:1立体声模拟输入复接器, 立体声DAC到线路输出动态翻番97dB,THD+N为-86dB,H类放大器.本文介绍了CS42L37主要特性,方框图, 典型连接框图以及CS42L37评估板主要特性, 评估系统方框图以及评估板详细电路图与智能音频CODEC应用框图.
The CS42L73 is a highly integrated, low-power, audio and telephony CODEC for portable applications such as smartphones and ultra mobile personal computers.
The CS42L73 features a flexible clocking architecture, allowing the device to utilize reference clock frequencies of 6, 12, 24, 13, 26, 19.2, or 38.4 MHz, or any standard audio master clock. Up to two reference/master clock sources may be connected; either one can be selected to drive the internal clocks and processing rate of the CS42L73.
Thus, multiple master clock sources within a system can be dynamically activated and de-activated to minimize system-level power consumption.
Three asynchronous bidirectional serial ports (Auxiliary, Audio, and Voice Serial Ports) support multiple clock domains of various digital audio sources or destinations. Three low-latency, fast-locking, integrated high-performance asynchronous sample rate converters synchronize and convert the audio samples to the internal processing rate of the CS42L73.
A stereo line input or two mono (one stereo) microphone (MIC) inputs are routed to a stereo ADC. The MIC inputs may be selectively pre-amplified by +10 or +20 dB. Two independent, low-noise MIC bias voltage supplies are also provided. A programmable gain amplifier (PGA) is applied to the inputs before they reach the ADC.
The stereo input path that follows the stereo ADC begins with a multiplexer to selectively choose data from a digital MIC interface. Following the multiplexer, the d...