| 主题：採用新的低成本FPGA實現大批量應用網路研討會 |
| 在线问答： |
| [主持人：ChinaECNet] |
各位聽眾（網友），上午好！歡迎參加中電網線上座談。今天，我們有幸邀請到Altera公司的專家就“採用新的低成本FPGA實現大批量應用網路研討會”舉行線上座談。在座談中，您可就您關心的問題與Altera公司的專家線上進行直接、即時的對話交流。中電網衷心希望通過大家的共同努力，不僅能夠增進各位聽眾（網友）對“採用新的低成本FPGA實現大批量應用網路研討會”的瞭解和掌握，而且能夠為大家事業的發展帶來裨益。 |
[2007-4-12 10:01:30] |
| [主持人：ChinaECNet] |
我們已經進入問答階段如果聽眾想重溫演講或內容可以點擊下面“回顧演示”重看演講。 |
[2007-4-12 10:38:02] |
| [问：sunnyyao] |
cycloneIII與CycloneII差異有哪些? |
| [答：Susan] |
CII is 90 nm porcesss and CIII is 65 LP nm process. CIII has more multiplier, more memory, higher density and lower power. New features, OCT and remote programming are added in. Also we enhance PLL. For more detail information, please go Altera websiet at www.altera.com or contact our local distributors. |
[2007-4-12 10:43:50] |
| [问：leonqin] |
Cyclone III和Spartan III 的比較,有什麼優勢? |
| [答：Alex] |
基本上，Spartan3是90nm的產品，而Cyclone3是65nm的產品，所以在價格、功耗、及性能上都有比較好的表現。 |
[2007-4-12 10:44:07] |
| [主持人：ChinaECNet] |
在此回答問題的專家是Altera公司的：Brenda Fong、Susan Chang、Vincent Cao、Sam Yang、Wes Chang、Alex Miao和Daniel Chiu。 |
[2007-4-12 10:44:33] |
| [主持人：ChinaECNet] |
各位觀眾，現在用戶提問很踴躍，專家正在逐一回答。請耐心等待您問題的答案，同一問題請不要多次提交。 |
[2007-4-12 10:45:50] |
| [问：nonstop0127] |
您好～
之前都是用貴公司的CPLD來建立系統，因為CPLD並不是用SRAM建構
所以沒有什麼線路保密的issue.
但是因為要轉換到FPGA上面來建立系統，而貴公司的FPGA採用的是SRAM的方式，那要如何確保外掛的EEPROM所儲存的線路保密問題呢？ |
| [答：Daniel] |
FPGA Design Security Using MAX II Reference Design
============================================
SRAM-based FPGAs are volatile devices. They require external memory to store the configuration data that is sent to them at power up. It is possible for the configuration bitstream to be captured during the transmission and used to configure other FPGAs. This form of intellectual property theft can cause revenue loss to the designer.
This reference design provides a solution to prevent FPGA designs from being copied. It allows the FPGA design to remain secure even if the configuration bitstream is captured. This is accomplished by disabling the functionality of the user design within the FPGA until handshaking tokens are passed to the FPGA from the MAX? II device. The MAX II devices are selected for generating the handshaking tokens because they are non-volatile and retain their configuration data during power down.
|
[2007-4-12 10:47:22] |
| [问：hpsun] |
Altera 的IDE軟體能否支援VHDL和VerilogHDL混合編程? |
| [答：Wes] |
可以 |
[2007-4-12 10:47:25] |
| [问：janking] |
我以前一直用MAX_PLUS平台，现在刚转Quatrs。我发现Quatrs的波形仿真和MAX_PLUS的波形仿真有很大不同，比较不习惯。对此您有什么建议让我尽快地掌握Quatrs的仿真；还有，MAX_PLUS里是不是不支持MAXⅡ的DEVICE？最后想说一下的是，在深圳很难买到MAX7000AE和MAXⅡ的DEVICE。 |
| [答：Susan] |
MAX_PLUS II does not support MAX II, only Quartus II. If you feel difficult for simulation, please contact our distributor for help. Also please cotanct our distributors at SZ for purchasing device. We have 5 distributors at SZ. Thanks. |
[2007-4-12 10:47:26] |
| [主持人：ChinaECNet] |
各位觀眾，現在用戶提問很踴躍，專家正在逐一回答。請耐心等待您問題的答案，同一問題請不要多次提交。 |
[2007-4-12 10:48:46] |
| [问：wujunhao] |
C3是否配備有Flash?如沒有,可外接多大容量的Flash? |
| [答：Wes] |
C3並沒有配備Flash，而外接Flash的容量大小，只要pincount足夠，並沒有任何限制。 |
[2007-4-12 10:51:43] |
| [问：hpsun] |
Altera公司能提供那些工具來估計FPGA的功耗?估計的精確性能達到多高%? |
| [答：Susan] |
In Quartus, we have power awareness for setting constraint. Also we have power play that you can estimate before place and route. After place and route, you can check power data again. For more further information, please contact our distributors. Thanks. |
[2007-4-12 10:51:47] |
| [问：nonstop0127] |
請問CycloneIII也是使用外部的Memory來載入線路嗎？如果是的話要如何確保線路的安全性？ |
| [答：Alex] |
是的，CycloneIII也是使用外部的Memory來載入線路。在Altera的官網上有一份關於確保線路的安全性的技術文件，有興趣的話可以參考，謝謝！ |
[2007-4-12 10:53:48] |
| [问：jameshcc] |
能否介紹Cyclone III的記憶體架構和記憶體容量?它們和Cyclone II有何區別? |
| [答：Susan] |
In CII, we have 4K bit per memory block and CIII we have 9K bit per memory block. The memory size increases in the blokc but the I/O number is still the same. This architecture is more efficient for video imaging processing like line buffer. |
[2007-4-12 10:55:00] |
| [问：chrisheu] |
可以運用在 ZigBee上面嗎? 要如何運用。 謝謝! |
| [答：Vincent] |
Yes, CIII can be used on Zigbee. The usage will depending on cusotmer applications.
For example, you can use CIII to perform DSP functions, filtering and modulations. Please check www.altera.com for reference design and our partner soltions. |
[2007-4-12 10:55:07] |
| [问：wwsmc] |
NOIS II如何實現乙太網控制? |
| [答：Vincent] |
In our megacore functions we have ethernet MAC IP available. It is under SOPC builder or invoke from megacore tool. It will be connected through our proprietary AVALON bus to NIOS II.
The MAC core will have interface to connect to external PHY. You can find documentation on our website or click on the megacore "documentation" link to obtain more information. |
[2007-4-12 10:59:21] |
| [问：larryheng] |
時鐘會消耗許多功率,如何對時鐘進行管理來降低功耗? |
| [答：Wes] |
QuartusII 會依據設計來降低功耗。若想要自行管理時鐘來降低功耗，則建議使用clock buffer with enable signal，將暫時不使用電路區塊的時鐘來源關閉。這樣的電源管理可說是目前降低功耗的主流方法。包括Intel的CPU也是使用這樣的方式來降低功耗。 |
[2007-4-12 11:00:29] |
| [问：liyanhua] |
请详细介绍一下此芯片的更新换代产品，即它是在哪个芯片的版本上升级的，主要住了哪些更改，谢谢！ |
| [答：Wes] |
CIII 是 CII的下一代產品，主要改進在於PLL的性能，更大的memory以及更低的功耗。同時因為製程的演進，所以die的面積更小，成本更低。 |
[2007-4-12 11:02:56] |
| [问：lzqing] |
Cyclone III和Xilinx 的Virtex 5都是 65nm FPGA器件,兩者在性能和應用上有什麼區別? |
| [答：Daniel] |
基本上CIII是low cost,low power,high function的FPGA,
CIII提供5K~120L LEs,比Spartans3(90nm)更具成本/效能競爭力.Virtex5L FPGA提供10k~115K ALMs,Altera 提供High performace StratixII/III 系列能比Virtex5有更好的效能優勢,歡迎跟wintech FAE洽詢詳細內容. |
[2007-4-12 11:03:24] |
| [问：willow_yang] |
FPGA的发展趋势与该公司产品未来发展的特色 |
| [答：Alex] |
目前可見FPGA的發展趨勢是以更新、更低的製程來開發高效率、低成本、低功耗的FPGA，而本次研討會的主題：Cyclone3即是看到此發展趨勢而研發的新產品。而Altera未來產品發展也將會以滿足客戶需求為優先而努力。 |
[2007-4-12 11:05:38] |
| [主持人：ChinaECNet] |
各位觀眾，現在用戶提問很踴躍，專家正在逐一回答。請耐心等待您問題的答案，同一問題請不要多次提交。 |
[2007-4-12 11:06:14] |
| [问：julian3280] |
如何才能消除設計過程中產生的毛刺對邏輯功能的影響？ |
| [答：Wes] |
這只能由變更設計來改善。glitch 主要是由於非同步訊號間 delay的時間不同所造成的，除非是在沒有delay的晶片上，這種問題才不會發生。
|
[2007-4-12 11:06:29] |
| [问：zhangrenfu] |
請問這款Cyclone III晶片的主要優勢表現在什麼方面?功耗做的如何？目前晶片功耗是個很重要的問題，也是晶片開發的瓶頸。 |
| [答：Daniel] |
CIII採TSMC nm製程,所以是一個low cost,low power ,high function的FPGA device.
CIII在功耗上的表現整體比CII減少27% |
[2007-4-12 11:07:50] |
| [问：julian3280] |
對FPGA來說,採用開關電源和LDO線性電源,那個會有優越性或更好? |
| [答：Wes] |
LDO當然是比較好的電源，但是功耗較大。
在一般使用經驗中，若沒有使用到FPGA內部的PLL，則switch power 和 linear power間的差異並不大。
但是一旦使用到PLL，則swtich power可能會增加PLL輸出的jitter。
但是在高速數位電路的應用中，layout, decoupling, PCB plane的配置對於FPGA運作的影響會遠大於power的品質。 |
[2007-4-12 11:11:46] |
| [问：hpsun] |
影響FPGA Cyclone III功耗的因素有那些?在設計階段如何降低FPGA的功耗? |
| [答：Susan] |
CIII is using 65 nm low power process and Quaturs
supports power aware feature, these help to lower the power consumption. For any critical part for power, you can set the power constraint. Please contact our distributors for further discussion. |
[2007-4-12 11:11:58] |
| [问：jetdata] |
Cyclone III是否有降功耗模式?總共有幾種?每種的效果如何? |
| [答：Vincent] |
CIII has a low power mode, which will take lower core voltage to save the power up to 30%. Our Quartus II software has "low power" option which can reduce further on the power consumption.
It is also advisable to use "clkena" on the PLL to save the dynamic power |
[2007-4-12 11:17:56] |
| [问：cthuang] |
現在消費類便攜設備特別注重節能降耗設計，請問C3在這方面有什麼獨到體系結構和電源管理措施？謝謝！ |
| [答：Susan] |
Since CIII is using 65 nm LP process, it has lower 30% power comparing our CII family. Aslo Quartus II supports power aware feature, it will help to minimize the power for your design. Please contact our distributors for further discussion. |
[2007-4-12 11:18:43] |
| [问：jintuhai2007] |
一般來說,漏電流隨工藝尺寸的降低而增加,C3採用65nm深亞微米技術,有什麼措施使C3的漏電流得以降低? |
| [答：Wes] |
C3的漏電流並沒有降低多少，只有改善氧化層來些微降低漏電流對晶片的影響。所以C3運作的時脈並沒有比C2快多少。 |
[2007-4-12 11:19:36] |
| [问：nonstop0127] |
CycloneIII的 DK-START-3C25N StarterKit 在貴公司的網站似乎是缺貨的狀態，什麼時候才會開始販賣呢？ |
| [答：Susan] |
You can book order right now. It will start shipping at the end of this month. We have promo pricing for USD $150 until 9/28. |
[2007-4-12 11:20:49] |
| [问：jerrytechstar] |
我司是首次想用Fpga設計新產品,以前都用ASIC.在台灣altera有無協力3rd party可配合協助設計呢? |
| [答：Wes] |
可以聯絡台灣茂綸股份有限公司。茂綸有眾多的FAE可以提供設計及使用FPGA的協助。 |
[2007-4-12 11:21:02] |
| [问：yao.fan] |
cyclone III 的dsp的单个乘法器的输入输出位宽是多少？最高工作频率是多少？ |
| [答：Daniel] |
You can use the CIII embedded multiplier block in one of two operational models:
(1) One 18-bit multiplier
(2) Up to two 9-bit independent multipliers
Up to 260-MHz performance. |
[2007-4-12 11:22:35] |
| [问：cthuang] |
C3和Quicklogic的一些低功耗fpga相比有什麼優點？ |
| [答：Vincent] |
CIII has the following advantages:
- Track record of delivering quality ICs to customers
- Excellent yield due to fabrication at TSMC
- Powerful and easy to use software to help customers to achieve design goal
- First in the industry to use TSMC 65nm low power process
There are a lot more features compared to other FPGA vendors. Please refer to our website for details
|
[2007-4-12 11:23:33] |
| [问：wujunhao] |
请问Cyclone III的IO是否兼容5V TTL？
请问Cyclone III是否需要外接Flash或PROM？
我想选低成本的又无需外接FLash或PROM的而且全球用货量又大的FPGA该选哪个？
对于低成本FPGA，我觉得外接一个Flash或PROM不但不安全而且另人觉得麻烦和反感，MAX II的价格低，性能不错，我觉得是个相当不错的CPLD。 |
| [答：Alex] |
1.Cyclone III的IO沒有兼容5V TTL
2.目前全球用貨量大的FPGA都是SRAM BASE，而SRAM BASE的FPGA都需要外接FLASH或PROM。基於這樣的條件，我會建議您用Altera的Cyclone系列的低成本FPGA。
3.謝謝您對MAX II的讚美，它的確是顆相當好的CPLD。 |
[2007-4-12 11:25:08] |
| [问：lzqing] |
請問專家,FPGA的低功耗和低 |
