Silicon Lab Si5372抖动衰减集成基准单PLL相干光学时钟解决方案

Silicon Lab公司的Si5372/71是单个PLL抖动衰减时钟,集成了两个外部(A级)和内部(J级)基准和该公司最新第四代DSPLL技术,以提供下一代相干光学应用的所需的性能.集成的基准不易受声发射影响,从而消除了外接晶振,从而节省了空间和成本.多达4个输出,满足高速整数模式,在相位抖动45fs-rms(1MHz-40MHz)高达2.75GHz.每个输出还可以配置成multiSynth模式任何频率输出,只要所增加频率灵活性是需要的,比如时钟正向误差修正(FEC)还能提供90 fs-rms典型的相位抖动(12 kHz-20 MHz).Si5372/71还具有低到0.001ppb步控制的DCO控制,并能锁住间隙时钟输入.输入频率范围,差分为8 kHz- 750 MHz, LVCMOS为8 kHz - 250 MHz,高速整数模式的最大输出频率2.75GHz,典型抖动45 fs-rms(1 MHz–40 MHz);Multisynth模式的最大输出频率717.5 MHz,典型抖动为90 fs RMS(12 kHz–20 MHz).器件满足以下规范ITU-T G.8262 (SyncE) EEC Options 1 and 2和ITU-T G.8262.1 (Enhanced SyncE) eEEC.主要用在相干光线路卡和模块(100G/400G/600G)以及高速数据转换器时钟.本文介绍了Si5372/71主要特性,功能框图,以及评估板Si5372 -EVB主要特性,功能框图,电路图和材料清单.
The Si5372/71 are single-PLL jitter attenuating clocks with both external (Grade A)and internal (Grade J) reference and Silicon Labs’ latest 4th generation DSPLL technologyto deliver the performance requirements of next generation coherent opticalapplications. The integrated reference is less susceptible to acoustic emissions andeliminates the need for external crystals that take up extra space and cost.
Up to four outputs can be assigned to high-speed integer mode capable of up to2.75 GHz at 45 fs-rms typical phase jitter (1 MHz–40 MHz). Each output may also beconfigured as multiSynth mode any-frequency outputs when added frequency flexibilityis required, such as clocking Forward Error Correction (FEC) while still delivering90 fs-rms typical phase jitter (12 kHz-20 MHz). The Si5372/71 also feature DCOcontrol with as low as 0.001 ppb step control and is able to lock to gapped clock inputs.
These devices are available with factory programming or can be programmedvia a serial interface with in-circuit programmable non-vol...