Silabs Si5386 12路无线抖动衰减时钟发生器解决方案

Silabs公司的Si5386是高性能12路任意频率无线抖动衰减时钟发生器,采用第四代DSPLL技术,差分输入频率7.68 MHz - 750 MHz, LVCMOS输入频率7.68 MHz- 250 MHz,差分输出频率(整数)高达2.94912 GHz,支持JESD204B.分数输出频率:差分高达735MHz,LVCMOS高达250MHz. 12 kHz–20 MHz的抖动80fs,输出格式可配置为LVDS, LVPECL,LVCMOS, CML和HCSL,输出信号幅度200 - 3200 mV,主要用在云无线接入网络PRH,小型基站,无线基站,有源天线系统,分布式天线系统等.本文介绍了Si5386 Rev. E和Si5386主要特性,框图,应用框图以及评估板Si5386E-E-EB主要特性,框图,电路图,材料清单和PCB设计图.
The Si5386 is a high performance, integer and fractional clock generator for wireless applications which demand the highest level of integration and phase noise performance. Based on Silicon Laboratories ’4th generation DSPLL technology, the Si5386combines frequency synthesis and jitter attenuation in a highly integrated digital solutionthat eliminates the need for external VCXO and loop filter components. A fixedfrequency crystal that provides frequency stability for free-run and holdover modes isintegrated within the package saving valuable PCB space. This all-digital solutionprovides superior performance that is highly immune to external board disturbancessuch as power supply noise.
Modern C-RAN remote radio heads and fixed wireless systems require a diverse setof clocks such as ADC/DAC, RF LOs, eCPRI/CPRI, and Ethernet clocks. TheSi5386 architecture is designed to deliver high-performance JESD204B DCLK andSYSREF clock pairs and flexible any-rate clocks for non-LTE clocks such as Ethernetand system reference clocks all from a single IC.
The Si5386 ’s internal DSPLL provides jitter attenuation and any-frequency multiplication of the selected input frequency without theneed for external VCXOs or loop filters. Input switching is controlled manually or automatically using an internal state machine. The oscillator circuit (OSC) provides a frequency reference which determines output frequency stability and accuracy while the device is inf...