NXP MPC5643L 32位MCU开发和三相BLDC/PMSM低压电源参考设计

关键词:Power Architecture MCU马达驱动 MPC5643L

时间:2016-2-8 09:46:21      来源:中电网

NXP公司的MPC5643L系列是基于32位Power Architecture的系统级芯片(SoC),采用高性能e200z4d双内核,工作频率高达120MHz,具有可变长度编码(VLE),存储器管理单元(MMU),带误差检测代码的4KB指令缓存和信号处理引擎(SPE),其增强特性适合用在嵌入使应用,特别是汽车应用控制器.本文介绍了MPC5643L主要特性,框图,评估板KITMPC5643DBEVM主要特性和硬件开发配置图,以及电路图,材料清单和PCB设计图.此外还介绍了采用MPC5643L MCU三相BLDC/PMSM低

NXP公司的MPC5643L系列是基于32位Power Architecture的系统级芯片(SoC),采用高性能e200z4d双内核,工作频率高达120MHz,具有可变长度编码(VLE),存储器管理单元(MMU),带误差检测代码的4KB指令缓存和信号处理引擎(SPE),其增强特性适合用在嵌入使应用,特别是汽车应用控制器.本文介绍了MPC5643L主要特性,框图,评估板KITMPC5643DBEVM主要特性和硬件开发配置图,以及电路图,材料清单和PCB设计图.此外还介绍了采用MPC5643L MCU三相BLDC/PMSM低压电源参考设计框图和电路图.
The MPC5643L series microcontrollers are system-on-chip devices that are built on Power Architecture technology and containenhancements that improve the architecture’s fit in embedded applications, include additional instruction support for digitalsignal processing (DSP) and integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digitalconverter, Controller Area Network, and an enhanced modular input-output system.
The MPC5643L family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. Itbelongs to an expanding range of automotive-focused products designed to address electrical hydraulic power steering (EHPS),electric power steering (EPS) and airbag applications. The advanced and cost-efficient host processor core of the MPC5643Lautomotive controller family complies with the Power Architecture embedded category. It operates at speeds as high as120 MHz and offers high-performance processing optimized for low power consumption. It capitalizes on the availabledevelopment infrastructure of current Power Architecture devices and is supported with software drivers, operating systems andconfiguration code to assist with users’ implementations.
MPC5643L主要特性:
• High-performance e200z4d dual core
— 32-bit Power Architecture® technology CPU
— Core frequency as high as 120 MHz
— Dual issue five-stage pipeline core
— Variable Length Encoding (VLE)
— Memory Management Unit (MMU)
— 4 KB instruction cache ...

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