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ADI公司的AD9652是双路16位取样速率高达310MSPS的模数转换器(ADC),双路ADC核具有多级流水线架构和输出误差修正逻辑,输入频率范围高达465MHz,极低的噪音-157.6dBFS,SFDR超过85dBFS,通路间隔离/串扰90dB,主要用在军用雷达和通信,多模式数字接收器(3G或4G), 测试测量和智能天线系统.
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ADI公司的AD9652是双路16位取样速率高达310MSPS的模数转换器(ADC),双路ADC核具有多级流水线架构和输出误差修正逻辑,输入频率范围高达465MHz,极低的噪音-157.6dBFS,SFDR超过85dBFS,通路间隔离/串扰90dB,主要用在军用雷达和通信,多模式数字接收器(3G或4G), 测试测量和智能天线系统.本文介绍了AD9652产品亮点和主要特性,功能框图,以及评估板AD-FMCOMMS6-EBZ主要特性,主要元件分布图,电路图和PCB元件分布图.
The AD9652 is a dual, 16-bit analog-to-digital converter (ADC) with sampling speeds of up to 310 MSPS. It is designed to support demanding, high speed signal processing applications that require exceptional dynamic range over a wide input frequency range (up to 465 MHz). Its exceptional low noise floor of −157.6 dBFS and large signal spurious-free dynamic range (SFDR) performance (exceeding 85 dBFS, typical) allows low level signals to be resolved in the presence of large signals.
The dual ADC cores feature a multistage, pipelined architecture with integrated output error correction logic. A high performance on-chip buffer and internal voltage reference simplify the inter-face to external driving circuitry while preserving the exceptional performance of the ADC.
The AD9652 can support input clock frequencies of up to 1.24 GHz with a 1, 2, 4, and 8 integer clock divider used to generate the ADC sample clock. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle. The 16-bit output data (with an overrange bit) from each ADC is interleaved onto a single LVDS output port along with a double data rate (DDR) clock. Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.
The AD9652 is available in a 144-ball CSP_BGA and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by pending U.S. patents.
AD9652产品亮点:
1. Integrated dual, 16-bit, 310 MSPS ADCs.
2. On-chip buffer simplifies ADC driver interface.
3. Operation from 3.3 V and 1.8 V ...
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