TI TMS320C6657 1.25 GHz DSP开发方案

TI公司的TMS320C6655/57是定点/浮点数字信号处理器(DSP),基于KeyStone多核架构,内核速度高达1.25GHz,集成了各种包括C66x内核,存储器子系统,外设和加速器在内的各种子系统,非常适用于高性能低功耗可编程应用，如任务关键型,测试与自动化,医疗影像以及基础设施设备等领域.本文介绍了TMS320C6655/57主要特性,框图以及C6657 Lite EVM评估板TMDXEVM6657L主要特性,方框图,电路图,PCB元件布局图和材料清单.
The TMS320C6655/57 DSP is a highest-performance fixed/floating-point DSP that is based on TI’s KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 1.25 GHz. For developers of a broad range of applications, such as mission critical, medical imaging, test and automation, and other applications requiring high performance, TI’s TMS320C6655/57 DSP offers up to 2.5 GHz cumulative DSP and enables a platform that is power-efficient and easy to use. In addition, it is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.
TI’s KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intra-device and inter-device communication that allows the various DSP resources to operate efficiently and seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a non-blocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity.
For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating point capability and the per core raw computational performance is an industry-leading 40 GMACS/cor...