Cirrus CS53L30高性能低功耗音频系统解决方案

Cirrus公司的CS53L30是高性能低功耗四路ADC,其ADC输入具有多种模式如模拟或数字麦克风或线路输入,差分,假差分或单端输入,数字处理特性包括音量控制,静音,可编程高通滤波器和两个数字麦克风接口等.主要用在语音识别系统,高端电话系统,录音机,数码相机和摄像机.本文介绍了CS53L30主要特性,框图, 模拟和数字麦克风连接图,以及评估板CBD53L30主要特性,框图,电路图和PCB元件布局图.
The CS53L30 is a high-performance, low-power, quad-channel ADC. It is designed for use in multiple-mic applications while consuming minimal board space and power.
The flexible ADC inputs can accommodate four channels of analog mic or line-input data in differential, pseudodifferential, or single-ended mode, or four channels of digital mic data. The analog input path includes a +10- to +20-dB boost and a –6- to +12-dB PGA. Digital mic data bypasses the analog gain circuits and is fed directly to the decimators. Four mic bias generators are integrated into the device. The device also includes two digital mic serial clock outputs.
The CS53L30 includes several digital signal processing features such as high-pass filters, noise gate, and volume control.The device can output its four channels of audio data over two I2S ports or a single TDM port. Additionally, up to four CS53L30s can be used to output up to 16 channels of data over a single TDM line. This is done by setting the appropriate frame slots for each device, and each device then alternates between outputting data and setting the output pin to high impedance.
The CS53L30 can operate as a serial port clock master or slave. In Master Mode, clock dividers are used to generate the internal master clock and audio clocks from either the 6-/12-MHz, 6.144-/12.288-MHz, 5.6448-/11.2896-MHz, or 19.2-MHz master clock.
The device is powered from VA, a 1.8-V nominal supply and VP, a typical battery supply. An internal LDO on the VA supply powers the device’s digital core. The VP supply powers the mic bias generators and the AFE.
The CS53L30 is controlled by an ...