ADI AD9277低成本低功耗医疗超声解决方案

ADI公司的AD9277是低成本低功耗小型容易使用的8路14位ADC,包括8路可变增益放大器(VGA)和低噪音放大器(LNA),抗混淆滤波器(AAF)和14位10MSPS到50MSPS本世纪末ADC以及可编相位旋转的I/Q解调器,主要用在医疗图像和超声波图像以及汽车雷达.本文介绍了AD9277主要特性和产品亮点,方框图, 超声波系统方框图以及AD9277评估板主要特性,评估板连接图,电路图,PCB布局图和材料清单.此外还介绍了ADI医疗超声解决方案方框图和信号链接图.
The AD9277 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA); an anti-aliasing filter (AAF); a 14-bit, 10 MSPS to 50 MSPS analog-to-digital converter (ADC); and an I/Q demodulator with programmable phase rotation.
Each channel features a variable gain range of 42 dB, a fully differ-ential signal path, an active input preamplifier termination, a maximum gain of up to 52 dB, and an ADC with a conversion rate of up to 50 MSPS. The channel is optimized for dynamic performance and low power in applications where a small package size is critical.
The LNA has a single-ended-to-differential gain that is selectable through the SPI. The LNA input noise is typically 0.75 nV/√Hz at a gain of 21.3 dB, and the combined input-referred noise of the entire channel is 0.85 nV/√Hz at maximum gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the input SNR is roughly 92 dB. In CW Doppler mode, each LNA output drives an I/Q demodulator. Each demodulator has inde-pendently programmable phase rotation through the SPI with 16 phase settings.
The AD9277 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.
The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO±) for capturing data on the output and a frame clock (FCO±) trigger for signaling a new output byte are provided.
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