Lattice LatticeECP3 FPGA视频协议开发方案

Lattice 公司的LatticeECP3 FPGA系列能提供高性能的特性如增强的DSP架构，高速SERDES和高速源同步接口。LatticeECP3系列采用65nm技术，有149K逻辑单元和支持多达486个用户I/O，可提供多达320个18x18乘法器以及各种并行I/O标准。广泛用于批量生产的对成本和功耗敏感的有线和无线基础设备以及各种多媒体设备。本文介绍了LatticeECP3 FPGA系列主要特性，LatticeECP3-35简化方框图以及LatticeECP3视频协议板主要特性，方框图和详细的电路图。
The LatticeECP3™ (EConomy Plus Third generation) family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications. The LatticeECP3 device family expands look-up-table (LUT) capacity to 149K logic elements and supports up to 486 user I/Os. The LatticeECP3 device family also offers up to 320 18x18 multipliers and a wide range of parallel I/O standards. The LatticeECP3 FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP3 devices utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distrib-uted and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and dual-boot capabilities. The pre-engineered source synchronous logic implemented in the LatticeECP3 device family supports a broad range of interface standards, including DDR3, XGMII and 7:1 LVDS. The LatticeECP3 device family also features high speed SERDES with dedicated PCS functions. High jitter toler-ance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular data protocols including PCI Express, SMPTE, Ethernet (XAUI,...