Lattice LatticeXP2 FPGA标准评估方案

Lattice 公司的LatticeXP2器件包括基于查找表（LUT）的 FPGA以及非易失闪存单元（flexiFLASH）。LatticeXP2系列器件的LUT从5K到40K，分布是RAM从10K到83Kb，EBR SRAM从166Kb到885Kb，EBR SRAM区块从9到48个，sysDSP从3个到8个，18x18乘法器从12个到32个，可用的I/O从172个到540个，GPLL从2个到4个。工作电压1.2V，主要用在对成本敏感的市场如消费类电子，汽车电子，医疗和工业，网络和计算。本文介绍了LatticeXP2系列主要特性，LatticeXP2-17器件简化方框图，LatticeXP2标准评估板主要特性和LatticeXP2标准评估板电路图。
LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells in an architec-ture referred to as flexiFLASH. The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with FlashBAK embedded block memory and Serial TAG memory and design security. The parts also support Live Update technology with TransFR, 128-bit AES Encryption and Dual-boot technologies. The LatticeXP2 FPGA fabric was optimized for the new technology from the outset with high performance and low cost in mind. LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support and enhanced sysDSP blocks. The ispLEVER® design tool from Lattice allows large and complex designs to be efficiently implemented using the LatticeXP2 family of FPGA devices. Synthesis library support for LatticeXP2 is available for popular logic synthesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeXP2 device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification. Lattice provides many pre-designed Intellectual Property (IP) ispLeverCORE™ modules for the LatticeXP2 family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing t...