Microchip PIC24F16KA102 XLP 16位MCU开发方案

Microchip 公司的PIC24F16KA102是极低16位MCU，采用改进型哈佛架构，32MHz时高达16MIPS，带4x PLL选择和多个除法选择的8MHz振荡器，17位x17位单周期硬件乘法器，32位x16位硬件除法器，16位x16位工作寄存器阵列，C编译器，运行模式的功耗低到8uA，深度睡眠模式的功耗为20nA，工作电压1.8V到 3.6V，住要用途包括RF传感器，数据采集器，温度传感器，电子门锁，测量传感器，遥控，安全传感器，智能卡和能量收获等。本文介绍了PIC24F16KA102主要特性，方框图以及 XLP 16位MCU开发套件主要特性和XLP 16位开发板详细电路图。
The PIC24F16KA102 family introduces a new line of extreme low-power Microchip devices: a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance. It also offers a new migration option for those high-performance applications, which may be outgrowing their 8-bit platforms, but do not require the numerical processing power of a digital signal processor.
PIC24F16KA102主要特性：
Power Management Modes:
• Run – CPU, Flash, SRAM and Peripherals On
• Doze – CPU Clock Runs Slower than Peripherals
• Idle – CPU Off, Flash, SRAM and Peripherals On
• Sleep – CPU, Flash and Peripherals Off and SRAM On
• Deep Sleep – CPU, Flash, SRAM and Most Peripherals Off
- Run mode currents down to 8uA typical
- Idle mode currents down to 2 uA typical
- Deep Sleep mode currents down to 20 nA typical
- RTCC 490 nA, 32 kHz, 1.8V
- Watchdog Timer 350 nA, 1.8V typical
High-Performance CPU:
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator with 4x PLL Option and Multiple Divide Options
• 17-Bit by 17-Bit Single-Cycle Hardware Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16-Bit x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture
Peripheral Features:
• Hardware Real-Time Clock and Calendar (RTCC):
- Provides clock, calendar and alarm functions