Lattice ispMACH 4000ZE超低功耗PLD开发方案

Lattice公司的 ispMACH 4000ZE是1.8V在系统编程的超低功耗PLD,包括有36个输入,16个宏单元通用逻辑区块(GLB). ispMACH 4000ZE中的I/O分成两组,每组有单独的电源,主要用在局域网唤醒,电源管理,LED控制, 袖珍键盘监视,电平转移和处理器通用I/O扩展.本文介绍了ispMACH 4000ZE主要特性, 功能方框图和ispMACH 4000ZE Pico 开发套件主要特性,以及电路图和材料清单(BOM).
ispMACH 4000ZE Family 1.8V In-System Programmable Ultra Low Power PLDs
The ispMACH 4000ZE devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which contain multiple I/O cells.
The I/Os in the ispMACH 4000ZE are split into two banks. Each bank has a separate I/O power supply. Inputs can support a variety of standards independent of the chip or bank power supply. Outputs support the standards compatible with the power supply provided to the bank. Support for a variety of standards helps designers implement designs in mixed voltage environments. In addition, 5V tolerant inputs are specified within an I/O bank that is connected to a V CCO of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces.
Designed for low-cost and ultra low power, Lattice’s ispMACH 4000ZE CPLDs can be used for Wake-On-LAN polling, power management, LED control, keypad monitoring, voltage level shifting and general purpose I/O expansion for processors.

图1.ispMACH 4000ZE功能方框图
ispMACH 4000ZE Pico 开发套件

图2.ispMACH 4000ZE Pico 开发套件外形图
This user’s guide describes how to start using the ispMACH 4000ZE Pico Development Kit, an easy-to-use plat­form for evaluating and designing with the LC4256ZE CPLD. Along with the evaluation board and accessories, this kit includes a pre-loaded Pico Power demonstration design. You may also reprogram the on-board LC4256ZE and ispPAC®-POWR6AT6 devices to review your own custom designs.
ispMACH 4000ZE Pico 开发套件主要特性:
The ispMA...