Lattice MachXO 非挥发PLD开发方案

Lattice 公司的MachXO系列是非挥发可无限次编程的可编程逻辑器件(PLD),LUT从256到2280. MachXO把CPLD和FPGA的特性集中在单个芯片上:胶合逻辑,总线桥,总线接口,上电控制和控制逻辑等. MachXO系列设计用于各种低密度的应用如消费类电子,汽车电子,通信,计算,工业和医疗.本文介绍了MachXO系列的主要特性和优势,以及MachXO系列PLD开发套件主要特性, 评估板方框图和详细电路图和所用元件清单.
The MachXO is optimized to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs: glue logic, bus bridging, bus interfacing, power-up control, and control logic. These devices bring together the best features of CPLD and FPGA devices on a single chip.
The MachXO family of non-volatile infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for applications traditionally implemented using CPLDs or low-capacity FPGAs. Widely adopted in a broad range of applications that require general purpose I/O expansion, interface bridging and power-up management functions, MachXO PLDs offer the benefits of increased system integration by providing embedded memory, built-in PLLs, high performance LVDS I/O, remote field upgrade (TransFRTM technology) and a low power sleep mode, all in a single-device.
Designed for a broad range of low density applications, the MachXO PLD family is used in a variety of end markets including consumer, automotive, communications, computing, industrial and medical.
MachXO主要优势:
Powers up in less than 1ms enabling precise control during system boot-up
No external configuration memory required reducing total system cost
Efficient cost effective data buffering
Integrated clock management reducing total system cost
Interface with multiple voltages and speed critical functions
Reduces standby power to <100uA
Allows remote field upgrades while the equipment operates
MachXO主要特性:
Non-volatile, Infinitely Reconfigurable
Instant-on–powers up in microseconds
Single chip, no external configuration m...